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1 mn101e56/57/76 series 8-bit single-chip microcontroller ? overview the mn101e series of 8-bit single-chip microcomputers (the memory expansion version of mn101c series) incorporate multiple types of peripheral functions. this chip series is well suited for camera, vcr, md, tv, cd, ld, printer, telephone, home automation, pager, air conditioner, ppc, fax machine, music instrument and other applications. this lsi brings to embedded microcomputer applications flexible, optimized hardware configurations and a simple efficient instruction set. mn101ef57 series has an internal 128 kb of rom and 6 kb of ram. peripheral functions include 5 external interrupts, 29 internal interrupts including nmi, 12 timer counters, 4 types of serial interfaces, a/d converter, d/a converter, lcd driver, 2 types of watchdog timer, data automatic function and buzzer output. the system con?guration is suitable for in camera, timer selector for vcr, cd player, or minicomponent. with 5 oscillation systems (high-speed (internal frequency: 20 mhz), high-speed (crystal/ceramic frequency: max. 10 mhz) / low-speed (internal frequency: 30 khz), low-speed (crystal/ceramic frequency: 32.768 khz) and pll: frequency multiplier of high frequency) contained on the chip, the system clock can be switched to high-speed frequency input (normal mode), pll input (pll mode), or to low-speed frequency input (slow mode). the system clock is generated by dividing the oscillation clock or pll clock. the best operation clock for the system can be selected by switching its frequency ratio by programming. high speed mode has the normal mode which is based on the clock dividing fpll, (fpll is generated by original oscillation and pll), by 2 (fpll/2), and the double speed mode which is based on the clock not dividing fpll. a machine cycle (minimum instruction execution time) in the normal mode is 200 ns when the original oscillation fosc is 10 mhz (pll is not used). a machine cycle in the double speed mode, in which the cpu operates on the same clock as the external clock, is 100 ns when fosc is 10 mhz. a machine cycle in the pll mode is 50 ns (maximum). ? product summary this datasheet describes the following model. model rom size ram size classi?cation package MN101EF76K 256 kb 10 kb flash eeprom version lqfp128-p-1818c mn101ef57g 128 kb 6 kb lqfp080-p-1414a tqfp080-p-1212f mn101ef56k 256 kb 10 kb qfp100-p-1818b note) dmod internal pull-up resistor is in only flash eeprom version. when using in-circuit emulator, it is necessary to connect the pull-up resistor on the circuit board. ver. bem publication date: february 2014
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3 ? features (continued) ? interrupts interrupts MN101EF76K 36 sets mn101ef57g 34 sets mn101ef56k 36 sets overrun interrupt non-maskable interrupt (nmi) ? ? ? timer interrupt timer 0 interrupt ? ? ? timer 1 interrupt ? ? ? timer 2 interrupt ? ? ? timer 3 interrupt ? ? ? timer 4 interrupt ? ? ? timer 6 interrupt ? ? ? timer 7 interrupt ? ? ? time-base interrupt ? ? ? timer 7 compare register 2 match interrupt ? ? ? timer 8 interrupt ? ? ? timer 8 compare register 2 match interrupt ? ? ? pwm over?ow interrupt ? ? ? pwm under ?ow interrupt ? ? ? timer 9 compare register 2 match interrupt ? ? ? 24h timer interrupt ? ? ? alarm match interrupt ? ? ? serial interrupt lin interrupt ? ? ? serial 0 interrupt ? ? ? serial 0 uart reception interrupt ? ? ? serial 1 interrupt ? ? ? serial 1 uart reception interrupt ? ? ? serial 2 interrupt ? ? ? serial 2 uart reception interrupt ? ? ? serial 3 interrupt ? ? ? serial 3 uart reception interrupt ? ? ? serial 4 interrupt ? ? ? serial 4 stop condition interrupt ? ? ? a/d interrupt a/d conversion interrupt ? ? ? data automatic transfer interrupt atc1 interrupt ? ? ? low voltage detection interrupt low voltage detection interrupt ? ? ? external interrupt irq0 (edge selection, noise ?lter connectable) ? ? ? irq1 (edge selection, noise ?lter connectable) ? ? ? irq2 (edge selection, both edge interrupt, noise ?lter connectable) ? ? ? irq3 (edge selection, both edge interrupt, noise ?lter connectable) ? ? ? irq4 (edge selection, both edge interrupt, noise ?lter connectable, key scan interrupt) ? ? ? ver. bem mn101e56/57/76 `
4 ? features (continued) ? timer counter: 12 sets general-purpose 8-bit timer 5 sets general-purpose 16-bit timer 2 sets general-purpose 16-bit timer 2 sets motor control 16-bit timer 1 set 8-bit free-run timer 1 set time-base timer 1 set baud rate timer 1 set 24h timer 1 set timer 0 (general-purpose 8-bit timer) square wave output (timer pulse output), added pulse (2 bits) type pwm output can be output to large current pin tm0iob, event count, simple pulse width measurement double-buffered compare register ( 1)* function in MN101EF76K and mn101ef56k clock source: fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fslow, external clock, timer a output real-time control: timer (pwm) output is controlled among the three values: "fixed to high", "fixed to low", or "hi-z" at falling edge of external interrupt 0 (irq0) timer 1 (general-purpose 8-bit timer) square wave output (timer pulse output), event count 16-bit cascade connection (connected with timer 0) double-buffered compare register ( 1)* function in MN101EF76K and mn101ef56k clock source: fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fslow, external clock, timer a output timer 2 (general-purpose 8-bit timer) square wave output (timer pulse output), added pulse (2 bits) type pwm output can be output to large current pin tm2iob, event count, simple pulse width measurement, 24-bit cascade connection (connected with timer 0, 1), timer synchronous output double-buffered compare register ( 1) clock source: fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fslow, external clock, timer a output real-time control: timer (pwm) output is controlled among the three values: "fixed to high", "fixed to low", or "hi-z" at falling edge of external interrupt 0 (irq0) timer 3 (general-purpose 8-bit timer) square wave output (timer pulse output), event count 16-bit cascade connection (connected with timer 2), 32-bit cascade connection (connected with timer 0, 1, 2) double-buffered compare register ( 1 ) clock source: fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fslow, external clock, timer a output timer 4 (general-purpose 8-bit timer) square wave output (timer pulse output), added pulse (2bit) type pwm output, event count, simple pulse width measurement clock source: fpll-div, fpll-div/4, fpll-div/16, fpll-div/32, fpll-div/64, fpll-div/128, fs/2, fs/4, fs/8, fslow, external clock, timer a output ver. bem mn101e56/57/76 `
5 ? features (continued) ? timer counter (continued) timer 6 (8-bit free-run timer, time-base timer) 8-bit free-run timer clock source: fpll-div, fpll-div/2 2 , fpll-div/2 3 , fpll-div/2 12 , fpll-div/2 13 , fs, fslow, fslow/2 2 , fslow/2 3 , fslow/2 12 , fslow/2 13 time-base timer interrupt generation cycle: fpll-div/2 7 , fpll-div/2 8 , fpll-div/2 9 , fpll-div/2 10 , fpll-div/2 13 , fpll-div/2 15 , fslow/2 7 , fslow/2 8 , fslow/2 9 , fslow/2 10 , fslow/2 13 , fslow/2 15 timer 7 (general-purpose 16-bit timer) clock source: fpll-div, fs, external clock, timer a output, serial 0 transfer clock output, timer 6 compare match cycle divided by 1, 2, 4, 16 hardware con?guration: double-buffered compare register ( 2) double-buffered input capture register ( 2) timer interrupt ( 2 vector) timer function: square wave output (timer pulse output), high-precision pwm output (cycle/duty continuous changeable) can be output to large current pin tm7iob, timer synchronous output, event count, input capture function (both edges operable) real-time control: timer (pwm) output is controlled among the three values: "fixed to high", "fixed to low", or "hi-z" at falling edge of external interrupt 0 (irq0) timer 8 (general-purpose 16-bit timer) clock source: fpll-div, fs, external clock, timer a output, timer 6 compare match cycle divided by 1, 2, 4, 16 hardware con?guration: double-buffered compare register ( 2) double-buffered input capture register ( 1) timer interrupt ( 2 vector) timer function: square wave output (timer pulse output), high-precision pwm output (cycle/duty continuous changeable) can be output to large current pin tm8iob, event count, pulse width measurement, input capture function (both edges operable) 32-bit cascade connection (connected with timer 7), 32-bit pwm output, input capture is available in 32-bit cascade timer 9 (motor control 16-bit timer) clock source: fpll-div, fs, external clock, timer a output divided by 1, 2, 4, 16 hardware con?guration: double-buffered compare register ( 2) timer interrupt ( 3 vector) timer function: square wave output (timer pulse output) can be changed to large current output, complementary 3-phase pwm output, triangle wave and saw tooth wave are supported, dead time insertion available, event count pin output control: pwm output control is possible by external interrupt 0 to 4 (ir q 0 to 4) ("hi-z", output data ?xed) timer a (baud rate timer) clock output for peripheral functions clock source: fpll-div divided by 1/1, 2, 4, 8, 16, 32, and fs divided by 2, 4 ver. bem mn101e56/57/76 `
6 ? features (continued) ? timer counter (continued) 24h timer clock source (usable frequency) fpll (4 mhz, 4.19 mhz, 5 mhz, 8 mhz, 8.38 mhz, 10 mhz, 16 mhz, 16.77 mhz, 20 mhz), fx (32.768 khz), frc (20 mhz, 16 mhz), frcs (30 khz) hardware con?guration: 0.5 seconds counter, minute counter, hour counter alarm compare register (in 0.5 seconds, in minutes, in hours) ( 1) timer interrupt ( 2 vector) timer function: interval function (interrupts every 0.5 seconds, 1 second, 1 minute, 1 hour, 24 hours) alarm function ? watchdog timer overrun detection cycle is selectable from fs/2 16 , fs/2 18 , fs/2 20 forced to reset inside lsi by hardware when a software processing error is detected twice ? watchdog timer2 overrun detection cycle is selectable from frcs/2 4 , frcs/2 5 , frcs/2 6 , frcs/2 7 , frcs/2 8 , frcs/2 9 , frcs/2 10 , frcs/2 11 , frcs/2 12 , frcs/2 13 , frcs/2 14 , frcs/2 15 forced to reset inside lsi by hardware when a software processing error is detected twice ? synchronous output function (timer synchronous output, interrupt synchronous output) latch data is output from port 8 at the event timing of synchronous output signal of timer 1, timer 2, timer 7, or external interrupt2 (irq2) ? buzzer output output frequency can be selected from fpll-div/2 9 , fpll-div/2 10 , fpll-div/2 11 , fpll-div/2 12 , fpll-div/2 13 , fpll-div/2 14 , fslow/2 3 , fslow/2 4 ? a/d converter MN101EF76K: 10-bit 24 channels mn101ef57g: 10-bit 12 channels mn101ef56k: 10-bit 24 channels ? d/a converter MN101EF76K: 8-bit 4 channels mn101ef57g: 8-bit 2 channels mn101ef56k: 8-bit 4 channels ? data automatic transfer: 1 system data is automatically transferred in all memory space external interrupt activation/internal event activation/software activation max. 255 byte continuous transfer serial continuous transmission and reception is supported burst transfer function (including interrupt emergency stop) ver. bem mn101e56/57/76 `
7 ? features (continued) ? serial interface MN101EF76K: 5 systems mn101ef57g: 4 systems mn101ef56k: 5 systems serial interface 0 (hardware lin / full duplex uart / synchronous serial interface) synchronous serial interface transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 4, timer a output divided by 1, 2, 4, 8, 16, external clock msb/lsb ?rst selectable, 1 to 8 bits of arbitrary transfer continuous transmission, continuous reception, continuous transmission and reception are available. full duplex uart (baud rate timer: selected from timer 0 to 4, or timer a) parity check, overrun error/framing error are detected transfer bits 7 to 8 are selectable hardware lin synch break generation, wake-up detection, synch break detection, synch field measurement are available serial interface 1 (full duplex uart / synchronous serial interface) synchronous serial interface transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4,timer 0 to 4, timer a output divided by 1, 2, 4, 8, 16, external clock msb/lsb ?rst selectable, 1 to 8 bits of arbitrary transfer continuous transmission, continuous reception, continuous transmission and reception are available. full duplex uart (baud rate timer: selected from timer 0 to 4, or timer a) parity check, overrun error/framing error are detected transfer bits 7 to 8 are selectable serial interface 2 (full duplex uart / synchronous serial interface) synchronous serial interface transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 4, timer a output divided by 1, 2, 4, 8, 16, external clock msb/lsb ?rst selectable, 1 to 8 bits of arbitrary transfer continuous transmission, continuous reception, continuous transmission and reception are available. full duplex uart (baud rate timer: selected from timer 0 to 4, or timer a) parity check, overrun error/framing error are detected transfer bits 7 to 8 are selectable serial interface 3 (full duplex uart / synchronous serial interface) * function in MN101EF76K and mn101ef56k synchronous serial interface transfer clock source: fpll-div/2, fpll-div/4, fpll-div/16, fpll-div/64, fs/2, fs/4, timer 0 to 4, timer a output divided by 1, 2, 4, 8, 16, external clock msb/lsb ?rst selectable, 1 to 8 bits of arbitrary transfer continuous transmission, continuous reception, continuous transmission and reception are available. full duplex uart (baud rate timer: selected from timer 0 to 4, or timer a) parity check, overrun error/framing error are detected transfer bits 7 to 8 are selectable ver. bem mn101e56/57/76 `
8 ? features (continued) ? serial interface (continued) serial interface 4 (multi master iic / synchronous serial interface) synchronous serial interface transfer clock source: fpll-div/2, fpll-div/4, fpll-div/8, fpll-div/32, fs/2, fs/4, timer 0 to 4, timer a output divided by 1, 2, 4, 8, 16, external clock msb/lsb ?rst selectable, 1 to 8 bits of arbitrary transfer continuous transmission, continuous reception, continuous transmission and reception are available. multi master iic 7, 10-bit slave address is settable general call communication mode is supported ? auto reset circuit ? low voltage detection circuit ? clock monitoring function ? led driver: 8 sets ? lcd driver segment output MN101EF76K: max. 55 pins (seg0 to seg54) mn101ef57g: max. 41 pins (seg0 to seg40) mn101ef56k: max. 55 pins (seg0 to seg54) segment output pins can be switched to i/o ports in 1 bit. * at reset, segment outputs are input ports. common output: 4 pins com0 to 3 can be switched to i/o ports in 1 bit. display mode selection static 1/2 duty, 1/2 bias 1/3 duty, 1/3 bias 1/4 duty, 1/3 bias lcd driver clock when the source clock is the main clock (fpll) 1/2 18 , 1/2 17 , 1/2 16 , 1/2 15 , 1/2 14 , 1/2 13 , 1/2 12 , 1/2 11 when the source clock is the sub clock (fslow) 1/2 9 , 1/2 8 , 1/2 7 , 1/2 6 timer 0 to 4, timer a output lcd power supply lcd power supply is separated from v dd5 . (can be used when v lc1 v dd5 ) external power supply voltage can be selectable. (supply voltage is supplied from v lc1 , v lc2 , and v lc3 ) internal dividing resistors (external power supply voltage is divided the voltage input to v lc1 by internal resistors.) ver. bem mn101e56/57/76 `
9 ? features (continued) ? ports ports MN101EF76K (pins) mn101ef57g (pins) mn101ef56k (pins) i/o ports 104 70 90 lcd segment 55 41 55 lcd common 4 4 4 serial interface communication 30 21 30 timer i/o 34 21 28 buzzer output 4 2 4 a/d input 24 16 24 external interrupt 10 5 5 lcd power supply 3 3 3 led driver (high-current) 8 8 8 high-speed oscillation 2 2 2 low-speed oscillation 2 2 2 d/a output 4 2 4 special function pins 10 10 10 operation mode input 3 3 3 reset input 1 1 1 analog reference voltage input 1 1 1 power supply 4 4 4 ver. bem mn101e56/57/76 `
10 ? pin description ? MN101EF76K (lqfp128-p-1818c) MN101EF76K (128lqfp top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 tm4ioa/an4/pa4 tm0ioa/an0/pa0 tm1ioa/an1/pa1 tm2ioa/an2/pa2 tm3ioa/an3/pa3 tm7ioa/an5/pa5 tm8ioa/an6/pa6 nrst/p27 xi/p90 xo/p91 osc1/p25 osc2/p26 v ss v dd5 mmod v dd18 dmod tm9ioa/an7/pa7 v ref+ atrst ron v ss ocd_data/led0/p00 ocd_clk/tm9iob/led1/p01 rxd0a/sbi0a/tm7iob/led2/p02 irq4b/pc4 pc5 pc6 irq1b/pc1 irq0b/pc0 irq2b/pc2 irq3b/pc3 p43/seg28/sbo0b/txd0b p36/seg32 p40/seg31/sbo3b/txd3b p41/seg30/sbi3b/rxd3b p42/seg29/sbt3b p44/seg27/sbi0b/rxd0b p45/seg26/sbt0b pd1/tm9od1b pd2/tm9od2b pd3/tm9od3b pd5/tm9od5b pd6 pd4/tm9od4b p57/seg23/buzzera p56/seg22/nbuzzera p55/seg21 p54/seg20 p46/seg25 p47/seg24 pd0/tm9od0b p53/seg19 p52/seg18/sbt1a p66/seg10/sbi2a/rxd2a p67/seg9/sbt2a p70/seg8/key0/sbi4a p63/seg13/tm3iob p64/seg12/tm4iob p65/seg11/sbo2a/txd2a p50/seg16/sbo1a/txd1a p51/seg17/sbi1a/rxd1a p61/seg15/da_c p62/seg14/tm1iob tm9od2a/sdo2/com1/p82 tm9od1a/sdo1/com0/p81 tm9od0a/sdo0/seg0/p80 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 n.c. sbt3a/da_d/led7/p07 acz0/irq0a/p20 acz1/irq1a/p21 irq2a/p22 irq3a/p23 irq4a/p24 sdo7/v lc1 /p87 sdo6/v lc2 /p86 tm9od5a/sdo5/v lc3 /p85 n.c. n.c. txd0a/sbo0a/tm8iob/led3/p03 sbt0a/tm2iob/tm0iob/led4/p04 txd3a/sbo3a/led5/p05 rxd3a/sbi3a/led6/p06 tm9od4a/sdo4/com3/p84 tm9od3a/sdo3/com2/p83 sda4a/sbo4a/key1/seg7/p71 n.c. n.c. n.c. n.c. sbt1b/key7/seg1/p77 rxd1b/sbi1b/key6/seg2/p76 txd1b/sbo1b/key5/seg3/p75 key4/seg4/p74 key3/seg5/p73 scl4a/sbt4a/key2/seg6/p72 p12/seg43/an22/tm1ioc p13/seg42/an23/tm3ioc p14/seg41/tm4ioc 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 n.c. pb3/seg54/an11 pb4/seg53/an12 pb5/seg52/an13 pb6/seg51/an14 pb7/seg50/an15 p95/seg49/an16/da_a p94/seg48/an17/da_b p93/seg47/an18 p92/seg46/an19 n.c. n.c. n.c. pb0/an8 pb1/an9 pb2/an10 p10/seg45/an20/tm0ioc p11/seg44/an21/tm2ioc p34/seg34/sbt4b/scl4b p35/seg33/sbi4b n.c. n.c. n.c. p15/seg40/tm7ioc/buzzerb p16/seg39/tm8ioc/nbuzzerb p30/seg38/sbo2b/txd2b p31/seg37/sbi2b/rxd2b p32/seg36/sbt2b p33/seg35/sbo4b/sda4b ver. bem mn101e56/57/76 `
11 ? pin description (continued) ? mn101ef57g (lqfp080-p-1414a, tqfp080-p-1212f) p57/seg22/buzzera mn101ef57g (80lqfp/tqfp top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 57 60 59 58 pb0/seg37/an8 pb1/seg36/ an9 pb2/seg35/an10 pb3/seg34/an11 p94/seg33/an12/da_a p93/seg32/an13 p92/seg31/an14 p33/seg30/an15/sbo4b/sda4b p34/seg29/sbt4b/scl4b p35/seg28/sbi4b p43/seg27/sbo0b/txd0b p44/seg26/sbi0b/rxd0b p45/seg25/sbt0b p46/seg24 p47/seg23 p56/seg21/nbuzzera p53/seg18 p52/seg17/sbt1a tm4ioa/an4/pa4 tm0ioa/an0/seg38/pa0 tm1ioa/an1/seg39/pa1 tm2ioa/an2/seg40/pa2 tm3ioa/an3/pa3 tm7ioa/an5/pa5 tm8ioa/an6/pa6 nrst/p27 xi/p90 xo/p91 osc1/p25 osc2/p26 v ss v dd5 mmod v dd18 dmod tm9ioa/an7/pa7 v ref+ atrst ron da_b/led7/p07 acz0/irq0/p20 acz1/irq1/p21 irq2/p22 irq3/p23 irq4/p24 sdo7/v lc1 /p87 sdo6/v lc2 /p86 tm9od5/sdo5/v lc3 /p85 v ss ocd_data/led0/p00 txd0a/sbo0a/tm8iob/led3/p03 sbt0a/tm2iob/tm0iob/led4/p0 4 ocd_clk/tm9iob/led1/p01 led5/p05 rxd0a/sbi0a/tm7iob/led2/p02 led6/p06 p73/seg5/key3 p74/seg4/key4 p75/seg3/key5/sbo1b/txd1b p76/seg2/key6/sbi1b/rxd1b p77/seg1//key7/sbt1b p80/seg0/sdo0/tm9od 0 p65/seg11/sbo2a/txd2a p66/seg10/sbi2a/rxd2a p67/seg9/sbt2a p64/seg12/tm4io b p70/seg8/key0/sbi4a p72/seg6/key2/sbt4a/scl4a p71/seg7/key1/sbo4a/sda4a p81/com0/sdo1/tm9od1 p82/com1/sdo2/tm9od2 p63/seg13/tm3io b p62/seg14/tm1io b p50/seg15/sbo1a/txd1a p51/seg16/sbi1a/rxd1a tm9od4/sdo4/com3/p84 tm9od3/sdo3/com2/p83 p55/seg20 p54/seg19 ver. bem mn101e56/57/76 `
12 ? pin description (continued) ? mn101ef56k (qfp100-p-1818b) p10/seg45/an20/tm0ioc p11/seg44/an21/tm2ioc p13/seg42/an23/tm3ioc p14/seg41/tm4ioc p15/seg40/tm7ioc/buzzerb p31/seg37/sbi2b/rxd2b p32/seg36/sbt2b p33/seg35/sbo4b/sda4b p34/seg34/sbt4b/scl4b p12/seg43/an22/tm1ioc p16/seg39/tm8ioc/nbuzzerb p30/seg38/sbo2b/txd2b mn101ef56k (100qfp top view) tm7ioa/an5/pa5 tm8ioa/an6/pa6 tm9ioa/an7/pa7 xi/p90 dmod xo/p91 osc1/p25 osc2/p26 vss vdd5 mmod vdd18 ron ocd_clk/tm9iob/led1/p01 vss ocd_data/led0/p00 tm1ioa/an1/pa1 tm0ioa/an0/pa0 tm2ioa/an2/pa2 tm3ioa/an3/pa3 tm4ioa/an4/pa4 p45/seg26/sbt0b p46/seg25 p47/seg24 p57/seg23/buzzera p70/seg8/key0/sbi4a p55/seg21 p51/seg17/sbi1a/rxd1a p64/seg12/tm4iob p65/seg11/sbo2a/txd2a p66/seg10/sbi2a/rxd2a p67/seg9/sbt2a p62/seg14/tm1iob p41/seg30/sbi3b/rxd3b p42/seg29/sbt3b p63/seg13/tm3iob irq3/p23 irq4/p24 sdo7/vlc1/p87 sdo6/vlc2/p86 tm9od5/sdo5/vlc3/p85 tm9od4/sdo4/com3/p84 tm9od3/sdo3/com2/p83 tm9od2/sdo2/com1/p82 tm9od1/sdo1/com0/p81 sbt1b/key7/seg1/p77 rxd1b/sbi1b/key6/seg2/p76 key4/seg4/p74 key3/seg5/p73 scl4a/sbt4a/key2/seg6/p72 pb0/an8 pb1/an9 pb2/an10 pb3/seg54/an11 pb4/seg53/an12 pb5/seg52/an13 pb6/seg51/an14 pb7/seg50/an15 p95/seg49/an16/da_a p94/seg48/an17/da_b p93/seg47/an18 p92/seg46/an19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 vref+ atrst p36/seg32 p35/seg33/sbi4b p43/seg28/sbo0b/txd0b p44/seg27/sbi0b/rxd0b p61/seg15/dc_c p50/seg16/sbo1a/txd1a p54/seg20 p53/seg19 p52/seg18/sbt1a txd0a/sbo0a/tm8iob/led3/p03 sbt0a/tm2iob/tm0iob/led4/p04 acz0/irq0/p20 acz1/irq1/p21 txd3a/sbo3a/led5/p05 rxd3a/sbi3a/led6/p06 nrst/p27 irq2/p22 rxd0a/sbi0a/tm7iob/led2/p02 sbt3a/da_d/led7/p07 tm9od0/sdo0/seg0/p80 txd1b/sbo1b/key5/seg3/p75 sda4a/sbo4a/key1/seg7/p71 p56/seg22/nbuzzera p40/seg31/sbo3b/txd3b ver. bem mn101e56/57/76 `
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202

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